In Spring, a young man’s fancy turns to thoughts of transmitters. Having recently completed a receiver, and with the weather starting to warm a bit, I’ve got an itch to actually get on the air and talk back to the stations whose code I can now (slowly, painfully) decode.
Re-purposing some hardware and code from my DDS VFO project, I’ve been working on on a digitally controlled CW transmitter based around an Si5351. This is by no means an original thought, and my designs are largely based on Qrp-Labs’ Ultimate3s Kit. You can check out that original design over on the QRP-Labs site, under the PCB assembly instructions.
Essentially, this transmitter uses an Si5351 DDS clock chip to directly synthesize the desired output frequency, at up to 200 Mhz. This frequency is then amplified by a simple FET amplifier to approximately a 1W output level, then passed through a low-pass filter and out to an antenna. The Si5351 is controlled over i2c by an Arduino Uno, which has an attached LCD, a rotary encoder, and a couple buttons for frequency and band control. The updated code for this project is on Github.
Here’s a block diagram of the transmitter:
The nice thing about this design is that the main frequency-dependent component is the low-pass filter; the Si5351 should be stable enough for CW contacts up to at least 50MHz. (Without an ovenized environment for the reference clock or some GPS disciplining or similar, there’s still a little drift and inaccuracy, but I don’t think it will be noticeable.) Above HF, I’d expect to see diminishing returns from the FET amplifier. But switching HF bands should just mean switching LPF filters and pressing a button on the VFO.
Here’s the circuit as constructed, up to where the LPF would go:
Let’s walk through the circuit starting from the signal generator and working out toward the antenna. The output of CLK0 on the Si5351 is coupled into the amplifier with a 100nF cap. This drives the gates of three J110 FETs, and is biased upward by a voltage divider formed by a 10K pot and a 4.7kOhm resistor between 5V and ground. The power end of this voltage divider is bypassed to ground with a 100nF cap.
Power for the amplifier is fed from a nominal 12V (or lower) through an RF choke, in this case 25T on an FT37-43, into the FET drains. A 100nF cap here helps further bypass RF to ground at this point. Output is taken off the drains through a final 100nF cap. The FET sources are grounded.
While an actual RF transistor like a BS170 would likely be ideal, I had a bunch of J110 FETs in my bin after my last trip to California, so that’s what I used. They’re only rated for about 300mW dissipated power, so I’ll need to be careful with my heat sinks and duty cycle until I can replace them with something a little more sturdy.
Preliminary results are encouraging – I hooked the output of the above circuit directly to a dummy load with no low-pass filter and ran the clock generator at 7.050MHz. I assessed power by reading off the peak voltage on an oscilloscope.I started with just 1 J110 and a 5V PA supply instead of 12V. This yielded about 9V peak-to-peak, or 200mW into 50 ohms. Installing the other two J110s bumped the output up to 10V P-P, or 250mW. Finally, after installing heat sinks on the FETs for safety and taking the supply voltage directly from a 12V SLA battery (~13.2V), the output hit 22V P-P, or 1.2W into 50 Ohms. This last reading was verified with the power meter on an MFJ versa tuner.
I’ll need to put a little elbow grease into low pass filters before putting this on the air, because even on a scope the signal looks a bit gnarly. But first the first time, I’m responsible for 1W of Homebrew RF power. Watch out!